1. Technical Field
The invention relates in general to semiconductor devices, and more particularly to systems and methods for accessing a magnetoresistive random access memory (MRAM) array.
2. Description of the Related Art
An MRAM memory device typically comprises a memory array having a plurality of bitlines and a plurality of wordlines intersecting the bitlines. The intersection of each wordline and bitline may comprise a magnetic memory element, such as a pseudo-spin valve (PSV) cell that is operable to store data. A PSV cell typically comprises a hard layer (or storage layer) and a soft layer (or sense layer), both of which are magnetic materials. Each layer may be magnetically aligned by currents running through the wordline and the bitline. A data value of 0 may be written to a PSV cell when the hard layer is magnetized to a first polarization by the wordline and bitline currents, and a data value of 1 may be written to the PSV cell when the hard layer is magnetized to a second polarization by the wordline and bitline currents.
To read a PSV cell, the magnitudes of the wordline and bitline currents are reduced so that only the soft layer changes polarization. A sense current is applied to the bitline, and the soft layer is magnetically aligned to a first state by a first current applied to the wordline, and then oppositely aligned to a second state by a second current applied to the wordline. Depending on polarization of the hard layer, the resistance of the PSV cell will decrease or increase as the soft layer switches alignment from the first state to the second state.
Typically, the MRAM device has analog current sources to provide the sense currents, and sense amplifiers to generate bit signals corresponding to a 0 or a 1 data value stored in the hard layer. Upon energization, these circuits undergo transient responses. For example, a bitline may be modeled as a string of series connected resistors with an inherent line capacitance. Thus, a signal transient proportional to a first order response having a time constant xcfx84=RC may be present. Other transients, such as transients associated with a current source applying the sense current to the bitline, may also be present. These transients may cause performance degradation and delays, thus increasing the time for memory access operations.
An MRAM device includes a memory array having a plurality of bitlines and a plurality of wordlines intersecting the bitlines. A plurality of memory elements are located at the intersections of the wordlines and the bitlines and are operable to store data. A bitline selection circuit is operable to select a first bitline and to provide a first sense current to the first bitline to generate a first reference signal. A wordline selection circuit is operable to sequentially select wordlines and to provide wordline currents to a selected wordline after the first reference signal has stabilized and while the first sense current is applied to the first bitline.
In an MRAM device array comprising a plurality of bitlines and a plurality of wordlines, the wordlines intersecting the bitlines and each intersection of the wordlines and bitlines comprising a memory element, a method for reading the memory elements of a corresponding bitline includes the steps of applying a first sense current to a first bitline to generate a first reference signal, stabilizing the first reference signal, and comparing the first reference signal to a second reference signal. Wordlines intersecting the bitline are sequentially selected, and corresponding memory elements at the intersections of selected wordlines and the first bitline are interrogated after the first reference signal has stabilized and while the first sense current is applied to the first bitline.
In an MRAM device array comprising a plurality of bitlines and a plurality of wordlines, the wordlines intersecting the bitlines and each intersection of the wordlines and bitlines comprising a memory element, the bitlines arranged in bitline pairs and each bitline of the bitline pair provided as an input to a differential amplifier, a method for reading the memory elements of a corresponding bitline pair includes the steps of applying a first sense current to a first bitline in a bitline pair to generate a first reference signal to the differential amplifier, and applying a second sense current to a second bitline in the bitline pair to generate a second reference signal to the differential amplifier. The first and second reference signals are stabilized, and wordlines intersecting the first bitline are sequentially selected. Corresponding memory elements at the intersection of selected wordlines and the first bitline are interrogated while the first and second sense currents are applied to the first and second bitlines.
A method of accessing a memory block in an MRAM array comprising a plurality of bitlines and a plurality of wordlines, the wordlines intersecting the bitlines and each intersection of the wordlines and bitlines comprising a memory element, includes the steps of determining corresponding addressed wordlines and corresponding addressed bitlines of the memory block and sequentially selecting corresponding addressed bitlines in the memory block. For each corresponding addressed bitline sequentially selected, a bitline current is applied to the selected addressed bitline, and after the addressed bitline has reached a steady state condition in response to the application of the bitline current, corresponding addressed wordlines intersecting the sequentially selected addressed bitline are sequentially selected. An access operation on the memory element corresponding to the sequentially selected addressed bitline and the sequentially selected addressed wordline is then performed.